The RISC-V project was started in 2010 by University of California, Berkeley and the reason it’s important is because it allows small device manufacturers to build RISC-V based systems without paying royalties. Similarly OpenFPGA is an open-source framework which automates and accelerates the development cycle for customizable FPGA architectures. This gives full freedom to small and medium size FPGA companies, and software developers to customize FPGA stacks
OSFPGA is determined to bring many students, colleges and start-ups on-board and democratize hardware design. So OSFPGA, in association with VLSI System Design (VSD) and Redwood EDA, presents a complete stack of overview courses starting from RISC-V ISA, moving on to RISC-V micro-architecture implementation from scratch then building mixed-signal design using RISC-V and implementing on commercial FPGA and finally porting RISC-V on OpenFPGA.
The whole course is divided in 3 sub-courses
RISC-V based MYTH (Microprocessors for you in thirty hours) (5-day course)
Mixed-signal RISC-V based SoC on FPGA (1-day course)
FPGA – Fabric, Design and Architecture (5-day course)
*Certificate of Completion will be provided by The Open-Source FPGA Foundation. It will include participants’ Lab reports Link and % Lab completion
All the best and happy learning
Course 1: RISC-V based MYTH (Microprocessors for you in thirty hours)
May 25th – May 29th
A beginner level 5-day workshop on “RISC-V based MYTH” (24hrs x 5days on VSD-IAT platform). When we say, “beginner level”, by end of the workshop you will understand:
1) RISC-V specs basics
2) RISC-V software basics
3) How to implement RISC-V basic specs using TL-Verilog
4) Simulate your own RISC-V core
This course is designed for anyone who is interested in learning more about hardware design. Students (new to digital logic or seasoned veteran) will take away new skills that can be applied immediately. No prior knowledge of digital logic design is required.
Course 2: Mixed-signal RISC-V based SoC on FPGA
This workshop helps you get started with a basic mixed-signal FPGA flow, which can be extended to any complex SoC. For people who have done RISC-V based MYTH workshop, you will find this workshop as an extension to the 5th Day, where RISC-V pipe-lined CPU coded in TL-Verilog is now converted to Verilog language and is a part of a mixed-signal SoC. If you are from ASIC/Physical design background, this workshop will complement your existing work, and you would really get to know the similarities and differences between ASIC and FPGA flow, which one is preferred under what conditions and why is it preferred. This single workshop connects VLSI students, analog designers, FPGA designers and ASIC designers. It is also an attempt to bring everyone on the same platform, and serves as a starting point for design verification
Course 3: FPGA – Fabric, Design and Architecture
June 1st – June 5th
In this workshop, we broadly cover 5 modules. The first module focuses on taking a digital design through Xilinx Vivado and programming it on the FPGA. We also demonstrate area, timing analysis, and post-implementation simulation. In the second module, we describe the OpenFPGA framework and demonstrate the VTR tool flow on two designs with an example architecture. Next, we repeat these tasks for a RISC-V based processor called RVMyth. We simulate RVMyth with a testbench through Vivado and program it on a Basys3 board. We then take it through the OpenFPGA framework through Skywater OpenSource FPGA (SOFA). We also demonstrate area, timing analysis, and post implementation simulation for the processor core after taking it through SOFA. Lastly, we summarize the area and timing results obtained by the design from Basys3 and VTR.
FAQ for courses:
Can I participate on my schedule in my timezone?
Yes, also you will be provided roughly 24×7 live support from mentors in various time zones over the duration of the workshop. We use Slack for live chat support and do also take up daily sync-up and one-to-one calls, as necessary.
Can experienced system designers join for refreshing concepts?
We welcome interested participants from all stages of their career. Even if you have learned logic design and CPU microarchitecture in the past, this course offers a modern perspective. TL-Verilog is a new and emerging standard and is useful for industry and academia alike. Get involved in revolutionizing your design/teaching/learning process!
I’m new to digital logic. Will I be able to complete the course?
This course teaches the basics of digital logic in the context of a modern design approach. So newcomers will learn something just as well as experienced designers. We have received positive feedback from learners ranging from 12 years of age to industry veterans, though we suggest this course for college age and above for folks on a technical path.
Can I access content after Workshop is finished ?
The main tool used in the workshop is the Makerchip.com online IDE, which is public and always open for development of open-source designs. You will also be given lifetime access to the slides and lab files after the workshop.
Do I need to install any software or tools to do labs?
No. Labs will be done on VSD-IAT cloud platform and Makerchip.com online IDE. You will be given access in your browser to a Linux Terminal, which has all necessary tools installed. Post workshop, we will provide scripts and templates to install or use the tools on your personal systems.
How is TL-Verilog different from Verilog?
TL-Verilog (Transaction-Level Verilog) is a new and emerging standard supporting “timing abstract” digital design, without which this course would not be possible. In addition to its powerful modeling constructs, it also eliminates legacy complexities of Verilog such as regs and wires, generate blocks, blocking vs. non blocking etc. It provides clean semantics that are easy to learn whether you already know Verilog or not. It integrates with existing commercial and open-source EDA tools by generating synthesizable (System)Verilog. Learn more at https://www.redwoodeda.com/tl-verilog
Basic knowledge of digital design and electronics.
Can VLSI freshers join this workshop?
Yes, it will be very helpful for VLSI freshers as they can learn about the Open-source FPGA fabric, design and architecture , which will enable them to explore this field on their own and learn. So as long as you are looking forward to learning something new and making a bright career in the field of VLSI, you are welcome.The workshop is designed in such a way that, we start with the basics first and then move on to advanced concepts. Have a look at curriculum in above registration link.
I am a 2nd year engineering student. Can I join this workshop?
Yes, If you are an experienced VLSI professional and want to learn about the OpenFPGA Fabric design, you are welcome to join this workshop.
Is there any certification provided for the participants?
Yes, Each participant with a completed Github repo will receive a certificate with performance score.
*Please Note: Registrants should register for each course individually i.e registering for one does not apply to the registration for the other two. Additionally, registrants have the option of taking one course at one time since OSFPGA will be offering the courses and the workshop on a rolling basis OR taking all of them together