Open Source IC Design
Tools Workshop

4-day workshop on Analog and Digital IC design flow using Open Source Tools

What will take place in this workshop?

  • Introduction to CMOS integrated circuits basics and Open Source tools design flow
  • Detailed illustration and hands-on experience of complete Open Source integrated circuit system design tools from Schematic to GDG and MPW prechecks
  • Tapeout submission using Open Source Skywater 130nm pdk on eFabless platform targeting Google sponsored MPW runs.

The Target Audience

  • BS students with basic electronics knowledge
  • Final Year EE Students interested in IC Design
  • Faculty Members
  • Industrial Professionals looking for IC Design skills

The Workshop Price

  • USD 250

The Schedule

  • From 16:00 to 20:00
  • London Park


  • Guest note
  • CMOS fabrication process
  • Open source tooIs
  • E–fabIess platform
  • Introduction: Analog & digital flow
  • Tools setup
  • From 16:00 to 20:00
  • London Park

Analog Design Flow

  • Schematic entry
  • Using Xschem
  • NGSpice simuIations
  • Layout design using Magic
  • DRC verification
  • LVS verification
  • Antenna ruIe checks
  • From 16:00 to 20:00
  • London Park

Digital Design Flow

  • OpenLane overview
  • Synthesis
  • Automatic pIacing & routing
  • CIock tree synthesis
  • Post synthesis
  • Layout simuIation
  • From 16:00 to 20:00
  • London Park

Signing OFF

  • Top IeveI integration
  • Submission for MPW
  • E–FabIess finaI and prechecks
  • E–FabIess tapeout jobs
  • Q&A session

Teaching and Technical Staff

Prof. Dr. Rashad Ramzan
Professor & Director RFCS2 Lab
Dr. Hassan Saif
Asst. Professor at FAST,
Engr. Hamza Atiq
Design Engineer
MS EE (IC Design)
Engr. Shahid Jamil
Design Engineer
Fellow MS IC Design
Engr. M Usman
Design Engineer
Fellow MS IC Design
Engr. Jafar
Design Engineer
Fellow MS IC Design

Our Team’s Credibility

  • Pioneer of Graduate IC design program in Pakistan with 44 full- time registered graduate students
  • Three designs were accepted in SSCS PICO (now Chipathon) Open Source Tapeout Contest and submitted for fabrication in Nov 2021
  • Two tape-outs were completed in September 2021 using TSMC 65nm node
  • Fully developed ICD lab with four full-time faculty members with degrees in IC design and cumulative experience of over a dozen IC tape-outs
  • Analog, Digital, and mixed signal design expertise on Open/Commercial Source tools.

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