AI & FPGA Committee

AI is emerging as a tool to enhance the performance of existing systems. As a result, various sectors such as health care, agriculture, and education are having a significant impact from AI. The Chip industry is no exception. Researchers and industrialists predict a tremendous increase in AI adaptation in the design flow in the future.

The interest in AI in FPGAs comes from two different communities. Firstly, FPGA developer community is interested in finding  out ways to speed up the FPGA development cycle by using AI. The user community is interested in both the use of AI to speed up writing of RTL and how FPGA solutions can be used for AI driven workloads.

Roles and Responsibilities

The charter of the AI and FPGA technical committee (AFC) of the Open Source FPGA Foundation ( OSFPGA) is to promote open source research and development on three vectors and hence will have three working groups.

  • AI driven fpga design tools working group will investigate faster simpler way of design fpga chips
  • AI driven fpga programming tools working group will investigate faster and better programming FPGA Given the similarities of RTL that users develop for a particular use case, AI can be used to develop faster and simpler ways of programming FPGAs. An ultimate goal could be to literally guess what the user wants to do and provide options to modify rather than write RTL from scratch or modify an existing RTL.
  • FPGAs for AI workloads working Group will investigate Use of FPGAs to drive AI workloads and innovative  AI driven solutions.  This will also cover FPGA based SoC accelerator architectures.

AFC will:

  • be open in membership and researchers, developers from all segments (companies, universities, research institutes, etc) are all welcome and encouraged to join from all countries of the world. We are very focused on diversity and inclusion therefore we will encourage team members from diverse and under privileged backgrounds to join us.
  • use standard operating principles of OSFPGA in its governance, election of officers and day to day operations.
  • be open source (including its working group work) and will be published on, GitHub and other repositories (as appropriate) to make it available for a worldwide audience.
  • encourage its members to publish their work in various conferences and journals around the world.
  • also collaborate with ETC to promote education of AI in FPGA by arranging webinars, seminars, and conferences worldwide.

Term and Election Process

Committee and Task Group chairs are elected for an annual term. There are no term limits.
In this section “Candidates” refer to people who want to be considered for a position. “Nominees” are sent to the AI & FPGA Committee for approval.
Existing Chairs and Vice Chairs may be candidates. Chairs must be non-individual members (Premier, Corporate). Vice Chairs can be individual members.
The election cycle is as follows:

  • Request for candidates by <date>
  • Candidates identified by <date + 14 days>
  • Nominees voted on at the next AI & FPGA Committee meeting

Who can vote

Any member of the AI & FPGA Committee can vote.