AI is emerging as a tool to enhance the performance of existing systems. As a result, various sectors such as health care, agriculture, and education are having a significant impact from AI. The Chip industry is no exception. Researchers and industrialists predict a tremendous increase in AI adaptation in the design flow in the future.
The interest in AI in FPGAs comes from two different communities. Firstly, FPGA developer community is interested in finding out ways to speed up the FPGA development cycle by using AI. The user community is interested in both the use of AI to speed up writing of RTL and how FPGA solutions can be used for AI driven workloads.
The charter of the AI and FPGA technical committee (AFC) of the Open Source FPGA Foundation (OSFPGA Foundation) is to promote open-source research and development on four vectors and hence will have four working groups.
AFC has been organized into four working groups.
1. Design Tools and Methods (DTM)
To investigate, propose, help in standards, benchmarks, and guide the development and interfaces of AI-based developmental tools for open source FPGAs.
2. Programming Tools and Methods (PTM)
To investigate, propose, help in standards, benchmarks, and guide the development of AI-based programming tools for open source FPGAs.
3. Use of FPGAs for AI (UOF)
To investigate, propose, help in standards, benchmarks, and guide the development of the use of open source FPGAs for AI workloads.
4. Optimal Architectures for AI (OAAI)
To investigate, propose, help in standards, benchmarks, guide the development of open source FPGAs which are optimal for AI workloads or specific AI workloads.
Committee and Task Group chairs are elected for an annual term. There are no term limits.
In this section “Candidates” refer to people who want to be considered for a position. “Nominees” are sent to the AI & FPGA Committee for approval.
Existing Chairs and Vice Chairs may be candidates. Chairs must be non-individual members (Premier, Corporate). Vice Chairs can be individual members.
The election cycle is as follows:
Any member of the AI & FPGA Committee can vote.