100% Open Source FPGA Tools: RTL-to-Bitstream in Minutes – A Hands-On Tutorial

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Description

The industry is about to reach a tipping point in the widespread adoption of Open Source FPGA tools. Historically, FPGA users have only had access to proprietary FPGA tools, essentially getting locked into a single vendor’s devices. Through significant investment by industry, government, and researchers, the advancement of Open Source FPGA tools has reached a threshold of commercial quality in terms of results and user experience.

Join us for this hands-on webinar where you will get an insight into the Yosys logic synthesis front-end tool integrated into the OpenFPGA project and Verilog-to-Routing (VTR ) backend tool that is one of the backbones of OpenFPGA, providing EDA support for FPGA fabrics, including packing, placement and routing. You will also learn about verification and tapeout toolchains enabling fully open-source FPGA fabric generation.

Speakers
  • Claire Wolf, Inventor of Yosys and Founder/CTO of YosysHQ
  • Vaughn Betz, Professor & NSERC/Intel Industrial Research Chair at University of Toronto
  • Xifan Tang, Research Assistant Professor at University of Utah & Lead Developer of OpenFPGA Project
Moderator

Shrikant Lohokare, CEO, OSFPGA Foundation

Sponsor

Rapid Silicon and QuickLogic Corporation