SALT LAKE CITY, Utah, May 25, 2021 – Open-Source FPGA Foundation (OSFPGA) has launched the “Tape Out World” initiative which is a key component of it’s push for democratizing silicon and purpose to promote design and manufacture of prototype FPGAs (and CPUs and other chips) world wide. In this effort OSFPGA will collaborate with Efabless Corporation, leveraging it’s ChipIgnite program that provides a pre-designed carrier-chip along with automated open-source design flow and full chip template making easy, affordable, and rapid implementation of custom chip design. The initiative will be operated by OSFPGA’s Tape Out World Committee with a global and modular approach and a roadmap for jumpstarting country specific programs, with Tape Out USA as default and others following in rapid succession.
At the high level, the idea of the Tapeout World and underlying country initiative is simple and scalable, where a few universities having at least two faculty researchers in chip design are identified in each country by a Country Champion who is a community or corporate member of OSFPGA. They are in turn enabled to organize at least two student projects all the way from design-through-tapeout on the EFabless platform. While the primary targets are universities, research institutes and startups can be supported. The tape outs are funded via sources vested in technology and ecosystem development identified by the country champion. OSFPGA will be announcing a series of such programs in Q2 2021 and beyond with several identified countries already in the pipeline process.
Program Package Includes:
Design & Tape Out via Efabless ChipIgnite Platform and Services
- Complete EDA design flow
- Automated physical implementation for digital designs
- Supports commercial EDA options as well
- Pre-designed packaging and test board
- 10 mm2 user design area
- 37 programmable IOs supporting digital and analog
- QFN or WCSP packaged parts based on shuttle
- 5 evaluation board assemblies
- 100, 300 or 1000 packaged parts
End-to-End Training via OSFPGA Education & Training Committee (ETC) Programs in collaboration with partners (VLSI System Design, Inc., and Redwood EDA Corporation)
How It Works:
- OSFPGA assigned Country Champion identifies at least two universities with at least two professors/ faculty researchers involved in microelectronics development and interested in chip design and tapeout projects.
- Respective professors identify at least two students to participate in the projects such that they benefit from direct experience in design and manufacture of simple chips.
- Professors choose from existing lab projects or pick from existing projects available on github and modify or pick elements of couple of different projects on github
- Professors work with the designated country champion as first point-of-contact.
- Country champion works on fundraising for projects ($19,000 i.e. $9,500 per chip for two chips per university) coordinating with but not limited to university affiliated bodies such as alumni associations.
- Professors identify students and projects (May – June)
- Country champion works on fundraising (May – June)
- Country champion coordinates slot reservation with EFabless designated point-of-contact (June)
- OSFPGA conducts training
- Execute project (July/Aug/Sept)
- $19,000 total for two chips per university
- $9,750 for 100 QFN or 300 WCSP parts per chip
- $200 gives guaranteed MPW slot reservation